Low etch pit density (epd) semi-insulating iii-v wafers

ABSTRACT

Systems and methods of manufacturing wafers are disclosed using a low EPD crystal growth process and a wafer annealing process are provided resulting in III-V/GaAs wafers that provide higher device yields from the wafer. In one exemplary implementation, there is provided a method of manufacturing a group III based material with a low etch pit density (EPD). Moreover, the method includes forming polycrystalline group III based compounds, and performing vertical gradient freeze crystal growth using the polycrystalline group III based compounds. Other exemplary implementations may include controlling temperature gradient(s) during formation of the group III based crystal to provide very low etch pit density.

CROSS REFERENCE TO RELATED APPLICATION(S)

This is a 371 filing of international PCT application No.PCT/US2008/005959, filed May 9, 2008, publication No. WO 2008/140763,and a continuation-in-part of application No. 12/506,209, published asUS2010/0001288A1, and claims benefit/priority of ancestor U.S.application Ser. No. 11/801,712, filed May 9, 2007, now U.S. Pat. No.7,566,641 and Chinese application 200810000938.8, filed Jan. 8, 2008,all of which are incorporated herein by reference in entirety.

BACKGROUND

1. Field

The present invention relates to semiconductor fabrication, and, moreparticularly, to systems and methods of manufacturing low etch pitdensity (EPD) group III-V wafers that can be used to manufacturedevices, such as Heterostructure Bipolar Transistors (HBT) andpseudo-morphic High Electron Mobility (pHEMT) devices, as well as towafers produced thereby.

2. Description of Related Information

It is well known in the group III-V/Gallium Arsenide (GaAs) industriesthat a etch pit density (EPD) level of a substrate is very important inminority carrier device reliability and in the yield of devices from thesubstrate. For example, regarding certain GaAs electronic devices, suchas hetero-structure bipolar transistors (HBTs) and pseudomorphic highelectron mobility transistors (pHEMTs), historically, substrate EPD isnot known to be a determining factor in device yield. However, it is nowknown that dislocations may bear relation to at least certain devicefailure, for example HBT device failures, as recently shown by Low et.al. (Low, T. S. et al., The Role of Substrate Dislocations in CausingInfant Failures in High Complexity InGaP/GaAs HBT ICs, 2007).Furthermore, light point defects (LPDs) [also known as localized lightscatterers (LLS) (see SEMI M54-0304—attached)] are undesirable for thesubsequent steps, such as epitaxial growth, which are performed on thesubstrates. Of particular importance is the reduction of crystal“non-particulate” LPDs which may occur as a result of the arsenicprecipitates in the grown ingots. For GaAs, these high LPDs typicallyoriginate as a result of the high arsenic overpressure used during thecrystal growth of the ingots.

Wafer annealing is well known. In addition, ingot annealing is known asdescribed in “Improved Uniformity of LEO Undoped Gallium ArsenideProduced by High Temperature Annealing” by Rumsby et al., GaAs ICSymposium, pp. 34-37 (1983).

Techniques for growing semiconductor crystals using a vertical gradientfreeze (VGF) and carbon doping are known, such as those disclosed inU.S. Pat. No. 6,896,729 to Liu et al. It is desirable to provide systemsand methods of manufacturing low etch pit density (EPD) GaAs and otherIII-V compound wafers, as well as the wafers themselves, using VGF andannealing techniques, and aspects consistent with the innovations hereinrelate to the provision thereof.

SUMMARY

Systems, methods, and wafers consistent with the invention relate tomanufacture of group III-V semiconductor devices using low EPD crystalgrowth and wafer annealing processes achieving group III-V (e.g., GaAs,etc.) wafers with higher device yields.

In one exemplary implementation, there is provided a method ofmanufacturing a group III based material with a low etch pit density(EPD). Moreover, the method includes forming polycrystalline group IIIbased compounds, and performing vertical gradient freeze crystal growthusing the polycrystalline group III based compounds. Other exemplaryimplementations may include controlling temperature gradient(s) duringformation of the group III based crystal to provide very low etch pitdensity.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory onlyand are not restrictive of the invention, as described. Further featuresand/or variations may be provided in addition to those set forth herein.For example, the present invention may be directed to variouscombinations and subcombinations of the disclosed features and/orcombinations and subcombinations of several further features disclosedbelow in the detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which constitute a part of thisspecification, illustrate various embodiments and aspects of the presentinvention and, together with the description, explain the principles ofthe invention. In the drawings:

FIG. 1 illustrates a method for fabricating group III-V wafers using VGFcrystal growth techniques consistent with certain aspects related to theinnovations herein.

FIG. 2 illustrates an EPD map for an exemplary wafer consistent withcertain aspects related to the innovations herein.

FIG. 3 illustrates the LPD distribution for a wafer that has not beenannealed.

FIG. 4 illustrates the LPD distribution for a wafer that has beenannealed according to the process of the invention consistent withcertain aspects related to the innovations herein.

FIGS. 5A and 5B illustrate methods for fabricating group III-V wafersusing crystal growth techniques consistent with certain aspects relatedto the innovations herein.

DETAILED DESCRIPTION OF EXEMPLARY IMPLEMENTATIONS

Reference will now be made in detail to the invention, examples of whichare illustrated in the accompanying drawings. The implementations setforth in the following description do not represent all implementationsconsistent with the claimed invention. Instead, they are merely someexamples consistent with certain aspects related to the innovationsherein. Wherever possible, the same reference numbers will be usedthroughout the drawings to refer to the same or like parts.

The systems and methods herein are applicable to the manufacture of GaAssubstrates and it is in this context that the innovations will bedescribed. The innovations have greater utility since they can be used,for example, to manufacture other types of substrates, such as indiumphosphide (InP), gallium phosphide (GaP) and other related III-Vcompound semiconductors.

FIG. 1 illustrates a method for fabricating GaAs wafers using a verticalgrowth furnace process 100. The process results in low light pointdefect, low etch pit density GaAs substrates. This process may also beused to fabricate indium phosphide (InP), gallium phosphide (GaP) orother related III-V compound semiconductors. The fabrication method is acombination of a very low EPD crystal growth process (described below inmore detail) and a wafer annealing process (described in more detailbelow) to achieve the very low LPD. The growth of very low EPD,semi-insulating GaAs (or other group III-V) wafers by the VGF processresults in high device yield in highly integrated GaAs (or other)circuits. According to aspects herein, wafer annealing processesconsistent with the innovations herein may yield very low LPD and/or, infurther aspects, controlled levels of Oxygen in the wafers. Low LPDwafers are desired by all semiconductor epitaxial growers since higherLPDs result in lower device yields from the substrates with the higherLPDs due to failure of devices made with the higher LPD substrate.

Returning to FIG. 1, the raw materials (102) are 7N grade (99.9999999%)Arsenic (As) and Gallium (Ga) from qualified vendors. The raw materialis directly used in a known poly synthesis process (104) to producepolycrystalline GaAs. Once the polycrystalline GaAs is generated,vertical gradient freeze (VGF) crystal growth occurs (106) as describedin more detail in U.S. Pat. No. 6,896,729 to Liu et al. which isincorporated herein by reference. Consistent with Liu et al., VGFfabrication according to the present innovations encompass crystalgrowth technology, apparatus, and processes whereby large single crystalingots are grown with a very high level of structural uniformity and lowdefect density. According to one exemplary implementation, controlledgrowth of GaAs is achieved by placing a dopant material in an ampouleoutside a growth crucible, not in contact with the molten charge. Sincethe dopant materials are separated from the melt or the internal wall ofthe crucible, the process is favorable for achieving a high singlecrystal growth yield. Exemplary VGF processes for achieving controlledincorporation of carbon in the growth of semi-insulating GaAs material,here, may include: (1) loading charges of GaAs raw materials into thecrucible, (2) placing carbon doping sources within, generally at a lowend of, the ampoule, (3) loading the crucible with the GaAs charges intothe ampoule, (4) evacuating/sealing under vacuum the ampoule containingthe dopant, the crucible, the GaAs charges, and B2O3 material, and (5)heating/melting the charge and then controlling the liquid-solidinterface, wherein control of the amount of the dopant and/or thetemperature are used to grow semi-insulating GaAs ingots with highuniformity and low defects. The VGF grown crystals may be tested (107)via Hall measurements and etch pit density measurements. As a result ofthe VGF Semi-insulating GaAs crystal growth process, the GaAs crystalhas an etch pit density of less than 900/cm²′ with the lowest EPDachieved about 600/cm² for 3″ diameter GaAs crystals. There areconventional processes that can produce Semi-insulating GaAs substrateswith the EPD as low as 900/cm², however none of the conventionalprocesses can produce GaAs or other similar wafers with less than900/cm² EPD. Thus, typical processes may achieve an EPD of 900/cm², butcannot achieve the lower EPD levels provided by this VGF process.

To achieve the low EPD, several VGF parameters are carefully controlled.The parameters may include the shape of the melt/crystal interface whichis controlled to be concave or convex to the melt front at ±2 mm,crystallization velocity from 2-16 mm/hour, and the temperature gradientat the melt/crystal interface between 0.1 to 2 degrees C/cm. Once theVGF crystals are grown (and optionally tested), a well known ingotshaping process (108) is conducted and the shaped ingot may also betested (109). Once the ingot is shaped, the ingot is sliced into wafers(110) and the wafers may be optionally tested using Hall and etch pitdensity measurements (111). The above processes may also be used toproduce InP and other III-V compound wafers. As a result of thisprocess, low EPD GaAs wafers are produced.

Once the low EPD wafers have been sliced from the ingot, a waferannealing process (112) is performed wherein the annealed wafers may betested (113). Instead of the typical three-stage annealing process, aone-stage annealing process is used. During that process the wafers areloaded vertically into a horizontal quartz boat and inserted in ahorizontal quartz ampoule along with the required Arsenic lumps. TheseArsenic lumps are carefully weighed to provide the needed vapor pressureat the annealing temperature to avoid any Arsenic dissociation from thesubstrates. The ampoule is then pumped down to a high vacuum level(<5E-3 Torr) and sealed. The ampoule and its contents are then insertedinto a horizontal 3-zone furnace and the heating of the ampoule and itscontents to the desired set (platform) temperature is initiated. Whenthe platform temperature (900 C to 1050C ) is reached it is heldconstant for several hours (10 to 48 hours). Subsequently, the heatingis decreased and the ampoule is allowed to cool down to room temperaturewithin a set time (6 to 24 hrs). During the one-stage annealing process,the oxygen level in the GaAs wafers is controlled by adjusting thevacuum level in the ampoule The annealing process conditions wereoptimized for heating rate, platform temperature and cooling rate toachieve very low LPD levels (<1/cm²). As a result of the annealingprocess, the wafer has light point defects as low as <1 cm⁻² withparticle size>0.3 μm. In addition, the wafer may have as low as <50particles/wafer having a particle size>0.3 μm for 6″ wafers.

Once the low EPD wafers are annealed and optionally tested for LPD andimpurity levels, a known wafer polishing process (114) is performed thatpolishes the low EPD wafers and the polished wafers may be optionallytested (115). Once the wafers are polished, the wafers are cleaned (116)and optionally tested (117) and then packaged for shipping to customers(118).

The EPD measurements are performed in accordance with SEMI M36-0699 andASTM Test Method F1404-92. An example of the EPD level as measured at 37points (each point having an area of 0.024 cm²) is shown in FIG. 2. Thisexample shows an average EPD of 695/cm². Note that the EPD is not evenlydistributed across the wafer and for this sample, the maximum EPD is1167/cm². All the numbers shown in FIG. 2 are actual counts of thenumber of EPDs—to obtain the EPD value, these numbers should be dividedby the unit area (namely, 0.024 cm²) to obtain the number per cm².

The LPD measurements are performed using a KLA-Tencor Surfscan 6220system. FIG. 3 shows the results of measurements made on an unannealedwafer. With no wafer annealing, the average LPD density is greater than164 cm⁻² (greater than 30,000 over the entire 6 inch diameter wafersurface). FIG. 4 shows the results of measurements made on an exemplaryannealed wafer. The average LPD density is less than 1 cm⁻² (less than50 over the entire 6 inch diameter wafer surface).

FIGS. 5A and 5B illustrate methods for fabricating group III-V wafersusing crystal growth techniques consistent with certain aspects relatedto the innovations herein. For example, FIG. 5A is consistent with amethod for manufacture a group III based material with a low etch pitdensity, the method comprising, forming polycrystalline group III basedcompounds 510, and performing vertical gradient freeze crystal growthusing the polycrystalline group III based compounds 520. Further, thecrystal growth process may include controlling temperature gradient(s)530. By way of example, such control may include controlling temperaturegradient of the group III based crystal during formation of the groupIII based crystal such that the group III based crystal has an etch pitdensity of less than about 900 per square centimeter. In anotherexemplary implementation, the crystal growth process may includecontrolling temperature gradient(s) associated with the group III basedcrystal during the vertical gradient freeze crystal growth wherein acrystal/melt temperature gradient is maintained between about 0.1 toabout 2 degrees Celsius/cm. Moreover, the growth process may alsooptionally include controlling melt/crystal interface 540, such ascontrolling one or both of a shape and/or a temperature gradient of amelt/crystal interface.

FIG. 5B illustrates an exemplary method of manufacturing a substratewith low light point defects, the method comprising forming a groupIII-V based substrate 550, annealing the group III-V based substrate560, for example, by using a single step annealing process, and removinga portion of the surface of the group III-V based substrate 570.Performed consistent with the innovations herein, a substrate may beformed having a light point defect density of less than about 1 persquare centimeter per gallium arsenide based substrate with a particlesize of equal to or greater than about 0.3 micrometers.

While the foregoing has been with reference to a particular embodimentof the invention, it will be appreciated by those skilled in the artthat changes in this embodiment may be made without departing from theprinciples and spirit of the invention, the scope of which is defined bythe appended claims.

1. A method for manufacture a gallium based material with a low etch pitdensity (EPD), the method comprising: forming polycrystalline galliumbased compounds; and performing vertical gradient freeze crystal growthusing the polycrystalline gallium based compounds, wherein the step ofperforming comprises: controlling temperature gradient(s) duringformation of the gallium based crystal such that the gallium basedcrystal has an etch pit density of less than about 900 per squarecentimeter.
 2. The method of claim 1 wherein the step of performingfurther comprises controlling one or both of a shape and/or atemperature gradient of a melt/crystal interface.
 3. The method of claim1 wherein the step of performing further comprises controllingmelt/crystal interface.
 4. The method of claim 3 wherein controlling themelt/crystal interface includes controlling temperature gradient of themelt/crystal interface.
 5. The method of claim 3 wherein controlling themelt/crystal interface includes controlling shape of the melt/crystalinterface.
 6. The method of claim 5 wherein controlling the melt/crystalinterface includes controlling temperature gradient of the melt/crystalinterface.
 7. The method of claim 1, wherein the crystal has an etch pitdensity of about 600 per square centimeter.
 8. The method of claim 7further comprising forming a gallium arsenide substrate from the galliumbased crystal.
 9. The method of claim 7 further comprising forming agallium phosphide or other gallium-group V substrate from the galliumbased crystal.
 10. The method of claim 1, wherein performing verticalgradient freeze crystal growth further comprises controlling a shape ofthe melt/crystal interface during the vertical gradient freeze crystalgrowth wherein the shape is concave or convex to a melt front at no morethan about ±2 mm.
 11. The method of claim 1, wherein performing verticalgradient freeze crystal growth further comprises controlling acrystallization velocity during the vertical gradient freeze crystalgrowth wherein the crystallization velocity is between about 2 and about16 mm/hour.
 12. The method of claim 1, wherein performing verticalgradient freeze crystal growth further comprises controlling temperaturegradient(s) associated with a melt/crystal interface during the verticalgradient freeze crystal growth wherein the temperature gradient at themelt/crystal interface is between about 0.1 to about 2 degreesCelsius/cm.
 13. A method for manufacture of a substrate with low lightpoint defects, the method comprising: forming a gallium arsenide basedsubstrate; annealing the gallium arsenide based substrate using a singlestep annealing; and removing a portion of the surface of the galliumbased substrate to form a gallium arsenide based substrate having alight point defect density of less than about 1 per square centimeterper gallium arsenide based substrate with a particle size of equal to orgreater than about 0.3 micrometers.
 14. The method of claim 13, whereinannealing the gallium arsenide based substrate further comprisescontrolling a heating rate during the annealing wherein the heating rateis about 900 to about 1050 degrees Celsius over about 10 to about 48hours.
 15. The method of claim 13, wherein annealing the galliumarsenide based substrate further comprises controlling a platformtemperature during the annealing wherein the platform temperature isabout 900 to about 1050 degrees Celsius.
 16. The method of claim 13,wherein annealing the gallium arsenide based substrate further comprisescontrolling a cooling rate during the annealing wherein the cooling rateis to room temperature in about 6 to about 24 hours.
 17. The method ofclaim 13 further comprising controlling oxygen into a surface of thegallium based substrate during the annealing process such that apredetermined oxygen content level is achieved.
 18. A gallium basedsubstrate, comprising: a substrate having an etch pit density of lessthan 900 per square centimeter using a vertical gradient freeze process;and the substrate having less than a total of about 120 light pointdefects per wafer having a light point defect particle size of greaterthan about 0.3 micrometers.
 19. The substrate of claim 18, wherein thesubstrate is gallium arsenide (GaAs).
 20. The substrate of claim 18,wherein the substrate is indium phosphide, gallium phosphide or otherIII-V compounds.
 21. A method for manufacture a group III based materialwith a low etch pit density (EPD), the method comprising: formingpolycrystalline group III based compounds; and performing verticalgradient freeze crystal growth using the polycrystalline group III basedcompounds, wherein the step of performing comprises: controllingtemperature gradient of the group III based crystal during formation ofthe group III based crystal such that the group III based crystal has anetch pit density of less than about 900 per square centimeter.
 22. Themethod of claim 21 further comprising forming indium phosphide or otherIII-V substrates from the group III based crystal.
 23. The method ofclaim 21, wherein performing vertical gradient freeze crystal growthfurther comprises controlling temperature gradient(s) associated withthe group III based crystal during the vertical gradient freeze crystalgrowth wherein a crystal/melt temperature gradient is maintained betweenabout 0.1 to about 2 degrees Celsius/cm.
 24. A method for manufacture agallium based material with a low etch pit density (EPD), the methodcomprising: forming polycrystalline gallium based compounds; andperforming vertical gradient freeze crystal growth using thepolycrystalline gallium based compounds, wherein the step of performingcomprises: controlling melt/crystal interface during formation of thegallium based crystal such that the gallium based crystal has an etchpit density of less than about 900 per square centimeter.
 25. The methodof claim 24 wherein controlling the melt/crystal interface includescontrolling one or both of shape and/or temperature gradient of themelt/crystal interface.